FIG. 1 shows a circuit diagram of an analog-digital pixel as taught in U.S. patent application Ser. No. 14/674,728, filed Mar. 31, 2015 (incorporated herein by reference). See, also, Raynor “A single-exposure linear HDR 17-bit hybrid 50 μm analogue-digital pixel in 90 nm BSI”, International Image Sensor Workshop, 2015 (also incorporated by reference).
The analog-digital pixel includes a photodiode coupled to a charge injector whose operation is controlled by a clock signal (FineConv Clk) and a control signal (End Frame). A charge integrator circuit is formed by an operational transconductance amplifier having a first input (VINN) and a second input (VRT) and an output (VOUT). A feedback capacitor (Cfb) is coupled between VOUT and VINN. VINN is further coupled to the photodiode to receive an input signal comprising the sum of a photodiode current (Ipd) and a feedback current (Ifb). The second input VRT receives a reset voltage. The output VOUT from the amplifier is coupled to an inverting input of a comparator. The non-inverting input of the comparator receives a reference voltage (VREF). An output of the comparator generates a digital signal (Count) for application to a clock input of a first counter (MS Counter). The digital signal output from the comparator is also referenced as the digital signal Comp that is provided to an input of an oscillator circuit (OSC). A switch is further coupled in parallel with the feedback capacitor. This switch is actuated by a first output of the oscillator circuit. A second input of the oscillator circuit receives a Start Frame control signal which is also applied to the clear (CLR) input of the first counter. A third input of the oscillator circuit receives an End Frame control signal that is also applied to an enable input of the charge injector. An output enable input (OE) of the first counter receives a control signal (Pixel Read). A second counter (LS Counter) has a clock input that receives the clock signal (FineConv Clk) and a clear input (CLR) that receives the logical inversion of the End Frame control signal. A count enable input (Count_EN) of the second counter receives the logical inversion of the Comp signal. An output enable input (Output_EN) receives the Pixel Read signal. The first counter is a ten-bit counter whose output bits form the most-significant Q[4:13] bits of a fourteen bit data bus. The second counter is a four-bit counter whose output bits form the least-significant Q[0:3] bits of the fourteen bit data bus. The digital signal on the data bus presents a digital value of the light sensed by the photodiode.
The analog-digital pixel of FIG. 1 operates in three phases. In a first phase, referred to as a sensor exposure phase, the Start Frame signal is asserted by an external control circuit and applied to the oscillator circuit and the first counter (causing a reset). The oscillator circuit responds to the Start Frame control signal by pulse actuating the switch to cause the feedback capacitor to be discharged, and the voltage at VOUT is set equal to the reset voltage at VRT. This operation is referred to as a resetting the charge integrator circuit. The photodiode responds to illumination by generating the current Ipd. This current is integrated by the charge integrator and the voltage at VOUT ramps. When the ramping VOUT voltage reaches the reference voltage VREF, the comparator changes state at its output (digital signal Count). The first counter responds to change in state of the Count signal by incrementing its counter value. The change in state of the corresponding Comp signal further causes the oscillator circuit to pulse actuate the switch and reset the charge integrator circuit. The foregoing process is then repeated, and each change in state at the output of the comparator causes the first counter to increment its count value. It will be noted that a slope of the ramping voltage at VOUT is correlated to the intensity of the light received by the photodiode. Thus, over a given time period for exposure of the photodiode, the number of times there is a change in state at the output of the comparator (with a corresponding increment of the count value) is proportional to the received light intensity.
At some later point in time the exposure phase ends (for example, in response to shutter closure or disconnection of the photodiode from the integrator). A fine count conversion phase is then commenced. In this regard, ending of the exposure phase may occur at a point in time where the VOUT voltage of charge integrator is somewhere between VRT and VREF. This is referred to in the art as a partial threshold state. The fine count conversion is performed to measure that voltage. During this phase, the first counter is disabled from responding to the Count signal.
The start of the fine conversion phase is indicated by the assertion of the End Frame signal by the external control circuit. The assertion of the End Frame signal produces three results: inhibiting the oscillator circuit from further resetting of the charge integrator, resetting the second counter and enabling the charge injector. The fine conversion clock (FineConv Clk) is applied to both the second counter and the charge injector. The charge injector responds to each pulse in the clock by injecting a small amount of charge into the VINN input of the charge integrator. Each injection of charge is accompanied by a corresponding incrementing of the count value in the second counter. The charge integrator integrates the injected charge and the output voltage VOUT continues to ramp. When the ramping VOUT voltage reaches the reference voltage VREF, the comparator changes state at its output (digital signal Count/Comp). The second counter responds to the change in state of the signal Comp by disabling further incrementing.
At this point, the readout phase is commenced. The output enable signal (Output_EN) is then asserted by the control circuit and the first and second counters output their respective count values. The combination of the output counter values from the first and second counters forms the fourteen-bit digital output signal indicative of the sensed illumination.
Reference is now made to FIG. 2 showing a block diagram for a stacked sensor configuration. A first wafer or die 10 includes a pixel array 12 with a row select circuit 14 and an array of comparators 16 associated with the columns. The outputs of the column comparators 16 are coupled to corresponding externally accessible contact structures (for example, vias or interconnections) 18 of the first die 10. A second wafer or die 20 includes an array of memory cells (SRAM) 22 coupled to corresponding externally accessible contact structures (for example, vias or interconnections) 24 of the second die 20. The externally accessible contact structures 18 and 24 are aligned so that when the first die 10 is stacked on the second die 20, an electrical connection can be made (for example, through a solder bump). A column select circuit 26 is coupled to the memory cells 22. Analog-to digital converter (ADC) data is output to a digital processing circuit 28 that functions to control the operation on die 20 through signal bus 30 and generate the data out.
Although FIG. 2 shows that the connection between die 10 and die 20 is made with one electrical connection per column, it will be understood that this is by example only. A one connection per row configuration is also possible.
The stacked configuration of FIG. 2 is advantageous in that analog circuitry is fabricated on the first die 10 and digital circuitry is fabricated on the second die 20.